1. Field of the Invention
The present invention relates to a method of forming a wafer backside interconnecting wire, and more particularly, to a method of forming a wafer level chip scale package (WLCSP) using the wafer backside interconnecting wire.
2. Description of the Prior Art
The package technologies of integrated circuits are substantially classified into two types: pin through hole (PTH) and surface mounting technology (SMT). Currently, the ball grid array (BGA) package is the most popular SMT type package. Please refer to FIG. 1, which is a schematic diagram of a BGA package 10. As shown in FIG. 1, the BGA package 10 includes a substrate 12, a die 14 bonded to the surface of the substrate 12 with silver glue 16, and a cap layer 18 which covers the die 14 and the surface of the substrate 12. The die 14 includes a circuit layout (not shown) and a plurality of metal bonding pads 20 electrically connected to the circuit layout (not shown). The BGA package 10 further includes a plurality of solder bumps 22 arranged in arrays on the bottom surface of the substrate 12. Each metal bonding pad 20 of the die 14 is electrically connected to a corresponding solder bump 22 using a conducting wire 24, and therefore the die 14 is connected to a printed circuit board (PCB) via the solder balls 22 for combining with other electronic devices.
As the critical dimension of semiconductor processes diminishes, the integrity of circuit layout improves day by day. Accordingly, the amounts of circuit layout I/O terminals increase as well. Under such a condition, the size of the BGA package 10 inevitably increases for accommodating the numerous metal bonding pads 20. However, this leads to some problems such as the warpage of the substrate 12. Therefore, the concept of chip scale package (CSP) is derived.
A CSP is a package having an area less than 1.5 times the area of a bare die, and the packages formed by various package technologies, e.g. by fine pinch ball grid array (FP BGA) technology or by flip chip (FC) technology, complying with this standard are included.
However, the CSP formed by any of the aforementioned technologies still has some disadvantages or limitations. Regarding the FP BGA technology, although an FP BGA package is consistent with the CSP definition, the FP BGA package suffers from the stress problem between the die and the substrate. In addition, the gap of two adjacent solder balls is limited, and an excessively small gap causes problems while welding the substrate and the PCB. Furthermore, if the die and the substrate are packaged by wire bonding, the area of the package cannot be further reduced. Regarding the FC technology, although the area of an FC package is smaller, the FC technologies cannot be applied to forming some devices, such as optical sensor devices, and print head devices.
In view of the above limitations, the applicant proposes a method of forming a wafer backside interconnecting wire, by which the area of the package is reduced to comply with the wafer level chip scale package (WLCSP) standard (the ratio of the area of package to bare chip is approximately equal to 1). In addition, this method is able to be applied for packaging the devices which require face-up packaging.